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May 1997
S IG N DES EW RN t ter a D FO 1 D E 53 5 C en sc EN or t OM M See HA l Supp il.com/t a REC ic rs inte c hn N OT r Te ww. ou rw IL o t act c on ERS T 8-IN i-88
(R)
HA5352
Fast Acquisition Dual Sample and Hold Amplifier
Features
* Fast Acquisition to 0.01% . . . . . . . . . . . . . . . 70ns (Max) * Low Offset Error . . . . . . . . . . . . . . . . . . . . . . . .2mV (Max) * Low Pedestal Error . . . . . . . . . . . . . . . . . . . . .10mV (Max) * Low Droop Rate . . . . . . . . . . . . . . . . . . . . . 2V/s (Max) * Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . 40MHz * Low Power Dissipation per Amp . . . . . . .220mW (Max) * Total Harmonic Distortion (Hold Mode) . . . . . . . -72dBc (VIN = 5VP-P at 1MHz) * Fully Differential Inputs * On Chip Hold Capacitor
Description
The HA5352 is a fast acquisition, wide bandwidth Dual Sample and Hold amplifier built with the Intersil HBC-10 BiCMOS process. This Sample and Hold amplifier offers the combination of features; fast acquisition time (70ns to 0.01%), excellent DC precision and extremely low power dissipation, making it ideal for use in multi-channel systems that require low power. The HA5352 comes in an open loop configuration with fully differential inputs providing flexibility for user defined feedback. In unity gain the HA5352 is completely self-contained and requires no external components. The on-chip 15pF hold capacitors are completely isolated to minimize droop rate and reduce the sensitivity of pedestal error. The HA5352 Dual Sample and Hold is available in a 14 lead PDIP and 16 lead SOIC packages saving board space while its pinout is designed to simplify layout.
Applications
* Synchronous Sampling * Wide Bandwidth A/D Conversion * Deglitching * Peak Detection * High Speed DC Restore
Ordering Information
PART NUMBER HA5352IP HA5352IB TEMPERATURE RANGE -40oC
o
PACKAGE 14 Lead Plastic DIP 16 Lead Plastic SOIC (W)
to
+85oC
o
-40 C to +85 C
Pinouts
HA5352 (300 mil SOIC) TOP VIEW HA5352 (PDIP) TOP VIEW
GND1 -IN +IN NC V1+IN2 -IN2 GND2
1 2 3 4 5 6 7 8 S/H2 S/H1
16 V1+ 15 S/H1 CONTROL 14 NC 13 OUT1 12 V2-
GND1 1 -IN1 2 +IN1 3 V1- 4 +IN2 5
14 V1+ 13 S/H1 CONTROL 12 OUT1 11 V210 OUT2 9 S/H2 CONTROL 8 V2+
11 OUT2 10 S/H2 CONTROL 9 V2+ -IN2 6 GND2 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 3-1
File Number
3394.5
Specifications HA5352
Absolute Maximum Ratings
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . +11V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V Voltage between S/H control and ground. . . . . . . . . . . . . . . . . +5.5V Output Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37mA Junction Temperature (Plastic Packages) . . . . . . . . . . . . . . +150oC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . +300oC (SOIC - Lead Tips Only)
Operating Conditions
Operating Temperature Range HA5352I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC TA +85oC Storage Temperature Range . . . . . . . . . . . . . -65oC TA +150oC Thermal Package Characteristics JA Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90oC/W SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95oC/W
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
Test Conditions: VSUPPLY = 5V; CH = Internal = 15pF, Digital Input: VIL = +0.0V (Sample), V IH = 4.0V (Hold). Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF, Unless Otherwise Specified HA5352I
PARAMETERS INPUT CHARACTERISTICS Input Voltage Range Input Resistance (Note 2) Input Capacitance Input Offset Voltage
TEMP
MIN
TYP
MAX
UNITS
Full +25oC +25oC +25oC Full
-2.5 100 -2 -3.0 -1.5 -2.5 60
500 15 2.5 80
+2.5 5 2 3.0 5 +1.5 +2.5 -
V k pF mV mV V/oC A A V dB
Offset Voltage Temperature Coefficient Bias Current Offset Current Common Mode Range Common Mode Rejection (2.5VDC, Note 3) TRANSFER CHARACTERISTICS Large Signal Voltage Gain (2.5VOUT)
Full Full Full Full Full
+25oC Full
95 85 -
108 40
-
dB dB MHz
Unity Gain -3dB Bandwidth TRANSIENT RESPONSE Rise Time (200mV Step) Overshoot (200mV Step) Slew Rate (5V Step) DIGITAL INPUT CHARACTERISTICS Input Voltage (High) VIH
+25oC
+25oC +25oC Full
0 88
8.5 105
30 -
ns % V/s
+25oC, +85oC -40oC
2.1
-
5.0
V
2.4 0
-
5.0 0.8
V V
Input Voltage (Low)
VIL
Full
3-2
Specifications HA5352
Electrical Specifications
Test Conditions: VSUPPLY = 5V; CH = Internal = 15pF, Digital Input: VIL = +0.0V (Sample), V IH = 4.0V (Hold). Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF, Unless Otherwise Specified (Continued) HA5352I PARAMETERS Input Current (VIL = 0V) Input Current (VIH = 5V) OUTPUT CHARACTERISTICS Output Voltage (R L = 510) Output Current (R L = 100) Full +25oC, +85oC -40oC Full Power Bandwidth (5VP-P, A V = +1, -3dB) Output Resistance - Hold Mode TOTAL OUTPUT NOISE, D.C. TO 10MHz Sample Mode Hold Mode SAMPLE MODE DISTORTION CHARACTERISTICS Total Harmonic Distortion VIN = 4.5VP-P, FIN = 100kHz VIN = 5VP-P, FIN = 1MHz VIN = 1VP-P, FIN = 10MHz Signal to Noise Ratio (RMS Signal to RMS Noise) Crosstalk VIN = 4.5VP-P, FIN = 100kHz +25oC +25oC +25oC +25oC -80 -74 -57 73 -76 -69 -52 dBc dBc dBc dB +25oC +25oC 325 325 Vrms Vrms Full +25oC -3 20 25 +3 V mA IIL IIH TEMP Full Full MIN -1 -1 TYP MAX +1 +1 UNITS A A
15 -
13 0.02
-
mA MHz
VIN = 5VP-P, FIN = 10MHz
+25oC
-
75
-
dB
HOLD MODE DISTORTION CHARACTERISTICS (50% Duty Cycle S/H) Total Harmonic Distortion VIN = 4.5VP-P, FIN = 100kHz, FS 100kHz VIN = 5VP-P, FIN = 1MHz, FS 1MHz VIN = 1VP-P, FIN = 10MHz, FS 1MHz Signal to Noise Ratio (RMS Signal to RMS Noise) VIN = 4.5VP-P, FIN =100kHz, FS 100kHz +25oC +25oC +25oC +25oC -78 -72 -51 70 -74 -67 -47 dBc dBc dBc dB
SAMPLE AND HOLD CHARACTERISTICS Acquisition Time 0V to 2.0V Step to 1mV 0V to 2.0V Step to 0.01% (200V) -2.5V to +2.5V Step to 0.01% (500V) +25oC +25oC +25oC 53 64 90 70 100 ns ns ns
3-3
Specifications HA5352
Electrical Specifications
Test Conditions: VSUPPLY = 5V; CH = Internal = 15pF, Digital Input: VIL = +0.0V (Sample), V IH = 4.0V (Hold). Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF, Unless Otherwise Specified (Continued) HA5352I PARAMETERS Droop Rate TEMP +25oC Full Hold Step Error (VIL = 0V, VIH = 4.0V, t R = 5ns) Hold Mode Settling Time (to 1mV) Hold Mode Feedthrough (5VP-P, 500kHz, Sine) EADT (Effective Aperture Delay Time) Aperture Time (Note 2) Aperture Uncertainty Aperture Match POWER SUPPLY CHARACTERISTICS Supply Current (per Amp) Total Supply Current PSRR (+V or -V, 10% Delta) NOTES: 1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operation under any of these conditions is not necessarily implied. 2. Derived from Computer Simulation only, not tested. 3. +CMRR is measured from 0V to +2.5V, -CMRR is measured from 0V to -2.5V. Full Full Full 60 20 40 74 22 44 mA mA dB Full 25oC 25oC +25oC +25oC +25oC +25oC MIN -2 -10 TYP 0.3 50 72 +1 10 10 30 MAX 2 +10 20 UNITS V/s V/s mV ns dB ns ns ps ps
3-4
HA5352 Die Characteristics
DIE DIMENSIONS: 2530 x 3110 x 525 25.4m 100 x 122 x 19 1mil METALLIZATION: Type: Metal 1: AlSiCu/TiW Thickness: Metal 1: 6kA 750A Type: Metal 2: AlSiCu Thickness: Metal 2: 16kA 1.1kA GLASSIVATION: Type: Sandwich Passivation Nitride - 4kA, Undoped Si Glass(USG) - 8kA, Total - 12kA SUBSTRATE POTENTIAL: VTRANSISTOR COUNT: 312
2kA
Metallization Mask Layout
HA5352
-IN1
GND1 GND1
V1+ V1+ V1+
S/H CONTROL1 +IN1
VOUT1 VOUT1
V1V1V1-
V2V2V2VOUT2
VOUT2 +IN2
S/H CONTROL2
-IN2
GND2 GND2
V2+
V2+ V2+
3-5

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